rev. 0.1 9/12 copyright ? 2012 by silicon laboratories AN694 AN694 w riting to f lash from f irmware on sim3 xxxx d evices 1. introduction this application note applies to the sim3cxxx, sim3uxxx, and sim3lxxx dev ice families. the flash memory on all silicon labs mcu devices is readable and writable from application code. this capability allows user software to store values, such as calibration constants or system pa rameters, to the flash and to implement a boot-loading feature in which user firmware can be updated in-system from a remote si te. the flash that is not used by application code ca n be treated like an eeprom, thus negating the need to connect an ex ternal eeprom to the device. this document starts with the basics of accessing flash from application c ode on any device, including device- specific details. then, it discusses advanced routines that can be developed from the basic routines. finally, it describes precautions to take when writing or erasing flas h. example code for the basic routines for all devices is installed with the precision32 sdk, which can be downloaded from www.silabs.com/32bit-software . 2. key points ?? the voltage supply monitor must be enabled in the vmonn module during flash write and erase operations. ?? the voltage supply monitor must be enabled as a reset source in the rstsrcn module during flash write and erase operations. note: any write or erase operations initiated while the voltage s upply monitor is disabled or the voltage supply monitor is disabled as a reset source will be ignored. ?? a lock and key sequence must be executed befor e executing a write or erase operation. the flash interface can be unlocked for one or multiple write or erase operations. ?? writes to the wrdata register wh ile the flash interface is locked or an incorrect unlock sequence will permanently lock the flash interface until the next device reset. ?? firmware should disable interrupts when writing or eras ing flash to ensure the flash interface accesses are sequential in time and take the minimum time possible. ?? for all flash write operations, firmware will stall unle ss operating from a memory space other than flash. ?? interrupts posted during a flash write or erase operation will be held p ending until the completion of the flash operation, after which they will be serviced in priority order.
AN694 2 rev. 0.1 3. flash essentials different device series have many simila rities for flash, including page sizes, lock bits, and the instructions used to read and write to flash. the main differences are the am ount of flash available, how the voltage supply monitor is enabled, how the voltage supply monitor is enabled as a reset source, and how registers are modified to allow flash writes and erases. although the core stalls duri ng flash write and erase operations, peripherals (usartn, saradcn, timern, etc.) remain active. in terrupts posted during a flash write or erase operation are held until the flash operation has completed, after which they are serviced in priority order. 3.1. flash organization the flash memory on most devices is organized into a set of 1024-byte pages. see the memory organization chapter of the device reference manual for specific inform ation. figures 1, 2, 3, and 4 show t he flash organization for the sim3uxxx devices. figure 1. sim3u16x flash memory map (256 kb) figure 2. sim3u15x flash memory map (128 kb) flash 0x0000_0000 0x0003_ffff 0x0004_0000 0x1fff_ffff reserved lock word 0x0003_fffc flash 0 x 0000_0000 0x0003_ffff 0x0004_0000 0x1fff_ffff reserved lock word 0x0003_fffc reserved 0x0001_ffff
AN694 rev. 0.1 3 figure 3. sim3u14x flash memory map (64 kb) figure 4. sim3u13x flash memory map (32 kb) 3.2. locking flash the flash can be locked by writing to the lock word in the flash memory region. a value of 0xffff_ffff or 0x0000_0000 at this location will unlock the flash. any other value writt en to this location will lock the entire flash from external (debugger) writes or reads until: ?? an erase operation is initiated from firmware. ?? an erase operation is initiated through the debug port (swd/jtag). ?? firmware writes 0x0000_0000 to the lock word. the location for the flash lock word will differ between devices, so consult the device reference manual for more information. flash 0x0000_0000 0x0003_ffff 0x0004_0000 0x1fff_ffff reserved lock word 0x0003_fffc reserved 0x0000_ffff flash 0x0000_0000 0x0003_ffff 0x0004_0000 0x1fff_ffff reserved lock word 0x0003_fffc reserved 0x0000_7fff
AN694 4 rev. 0.1 3.3. device-specific notes various mcus have features that require consideration when accessing flash. 3.3.1. sim3cxxx, sim3uxxx, and sim3lxxx flash lock and key all sim3cxxx, sim3uxxx, and sim3lxxx devices' writes and erases to fl ash are protected with a lock and key function. the flash lock and key register (flashctrln) must be written with the correct key codes in sequence before flash operations may be performed. the key codes are: 0xa5, 0xf1 for a single write or erase operation, and 0xa5, 0xf2 for multiple writes or erase operations. the timing does not matter, but the codes must be written in order. if the key codes are written out of order or th e wrong codes are written, fl ash writes and erases will be disabled until the next system reset. flash writes and er ases will also be disabled if a flash write or erase is attempted before the key codes have been written properly. for a single write or erase, the flash lock resets after each write or erase; the key codes must be written agai n before a following flash operation can be performed. for multiple writes or erases, the flash remains unlocked until the lock sequence is written (0xa5, 0x5a); the key codes do not need to be written before a following flash operation can be performed. 3.3.2. sim3cxxx, sim3uxxx, and sim3lxxx flash read timing the sim3cxxx, sim3uxxx, and sim3lxxx devices require that the speed mo de (spmd) and the read-store enable (rdsen) bits be set appropriately, depending on the ah b frequency. in addition, the flash read timing mode (flrtmd) bit can be configured to save power at slower clock frequencies. see the flashctrln chapter in the device's reference manual for detailed information on the read timing ranges. 3.3.3. sim3cxxx, sim3uxxx, and sim3lxxx vdd high threshold the sim3cxxx, sim3uxxx, and sim3lxxx devices have tw o settings for the vdd monitor threshold: standard and high. the high setting in creases the vdd low (early warning) and vdd reset thresholds by approximately 300 mv. the high setting is recommended when operating at faster ahb clock speeds. see the vmonn chapter in the device's reference manual for detailed information on enabling the high threshold. 3.4. flash write and erase operations the basic write operation writes a single half-word to fl ash. the erase operation applies to a full page of flash. flash write and eras e operations on silicon labs mcu devices are accomplished by using the wrdata and wraddr registers within th e flashctrln module. the setting of the eraseen field within the flashctrln module determines whether a write or an erase will execute. flash erase oper ations occur on page boundaries. the erase operation sets all the bits in the flash page to logic 1. flash write operations, which clear bits to logic 0, occur on single-byte boundaries. to su ccessfully complete a write to flash, the target bytes must be erased to 0xffff because the write instruction ca n only clear bits in a half-word. 3.5. flash read operations the basic read operation reads a single word from flash. flash read operations are accomplished by reading an address within the flash region of the device memory m ap. see the memory organization chapter in the device's reference manual for detailed information on the flash region boundaries.
AN694 rev. 0.1 5 4. basic flash operations the basic procedure for basic flash operations is the same on all devices. so me devices require setting additional registers to enable flash operations. the procedures in th is section include the except ions for the various device families. the code that implements th ese routines for eac h device family is in the flashctrl examples, which are installed with the precision32 sdk. 4.1. reading a single half-word 1. disable interrupts. 2. read the byte. 3. restore interrupts, if originally enabled. 4.2. writing a single half-word all bits, fields, and registers referred to in this sequence are in the flashctrln module. 1. ensure the voltage supply monitor is enabled and enabled as a reset source (device reset sources and vmonn modules). 2. disable erase operations (eraseen = 0). 3. write the destination ad dress to the wraddr register. 4. disable interrupts. 5. write the initial un lock value to key (0xa5). 6. write the single unlock value to key (0xf1). 7. write the data half-word to wrdata in right- justified format. 8. (optional) if executing code from a memory space other than flash, poll on the busyf flag until hardware clears it to 0. 9. enable interrupts. 4.3. writing multiple half-wor ds to sequential flash addresses to write a sequential set of bytes to flash, code should execute from a memory space other than flash. all bits, fields, and registers referred to in this sequence are in the flashctrln module. 1. ensure the voltage supply monitor is enabled and enabled as a reset source (device reset sources and vmonn modules). 2. disable erase operations (eraseen = 0). 3. write the initial destinati on address to the wraddr register. 4. enable sequential writes (sqwen = 1). 5. disable interrupts. 6. write the initial un lock value to key (0xa5). 7. write the multiple unlock value to key (0xf2). 8. write the data half-word to wrdata in right- justified format. 9. (optional) poll on the bursts flag until the buffer has room for more data. if code is executing from ram, this allows the core to perform other actions until a write operation completes and the buffer has room. the ahb bus will automatically stall until the operation completes if firmware writes data to wrdata when the buffer is full. 10. repeat steps 8 and 9 until all data is written. ha rdware automatically increments the wraddr field by 2 after each write operation. 11. (optional) if executing code from a memory space ot her than flash, poll on the busyf flag until hardware clears it to 0. 12. write the multiple lock value to key (0x5a). 13. enable interrupts.
AN694 6 rev. 0.1 4.4. writing multiple half-wor ds to non-sequential flash addresses all bits, fields, and registers referred to in this sequen ce are in the flashctrln module . to write multiple bytes to non-sequential addresses in flash: 1. ensure the voltage supply monitor is enabled and enabled as a reset source (device reset sources and vmonn modules). 2. disable erase operations (eraseen = 0). 3. disable interrupts. 4. write the initial un lock value to key (0xa5). 5. write the multiple unlock value to key (0xf2). 6. write the destination address to wraddr. 7. write the data half-word to wrdata in right- justified format. 8. (optional) if executing code from a memory space other than flash, poll on the busyf flag until hardware clears it to 0. 9. repeat steps 6, 7, and 8 until all data is written. 10. write the multiple lock value to key (0x5a). 11. enable interrupts. 4.5. erasing a flash page all bits, fields, and registers referred to in this sequence are in the flashctrln module. to erase a page of flash: 1. ensure the voltage supply monitor is enabled and enabled as a reset source (device reset sources and vmonn modules). 2. write the address of a byte in the flash page to wraddr. 3. enable erase op erations (eraseen = 1). 4. disable interrupts. 5. write the initial un lock value to key (0xa5). 6. write the single unlock value to key (0xf1). 7. write any value to wrdata in right-ju stified format to initiate the page erase. 8. (optional) if executing code from a memory space other than flash, poll on the busyf flag until hardware clears it to 0. 9. enable interrupts. 4.6. erasing multiple flash pages all bits, fields, and registers referred to in this sequence are in the flashctrln module. to erase multiple pages of flash: 1. ensure the voltage supply monitor is enabled and enabled as a reset source (device reset sources and vmonn modules). 2. enable erase op erations (eraseen = 1). 3. disable interrupts. 4. write the initial un lock value to key (0xa5). 5. write the multiple unlock value to key (0xf2). 6. write the address of a byte in the flash page to wraddr. 7. write any value to wrdata in right-ju stified format to initiate the page erase. 8. (optional) if executing code from a memory space other than flash, poll on the busyf flag until hardware clears it to 0. 9. repeat steps 6, 7, and 8 for each page.
AN694 rev. 0.1 7 10. write the multiple lock value to key (0x5a). 11. enable interrupts. 4.7. example code implementation notes the flashctrl example code that is installed with the precision32 sdk contains functions that can be copied and pasted into applications. these functions can be modifi ed as needed but should be used as a starting point for flash write and erase operations. 5. flash write and erase guidelines the following guidelines are strongly recommended for any system containing routines that write or erase flash from code. 5.1. voltage supply maintenance and the voltage supply monitor 1. if the system power supply is subject to voltage or current ?spikes?, add sufficient transient protection devices to the power supply to en sure that the supply voltages listed in the absolute maximum ratings table in the device data sheet are not exceeded. 2. if the device has a minimum voltage supply rise time specification, ensure that it is met. if the system cannot meet the rise time specification, add an external voltage supply browno ut circuit to the resetb pin of the device that holds the device in reset until th e voltage supply reaches the vdd high supply monitor threshold and re-asserts resetb if the voltage supply drops below the vdd high supply monitor threshold. 3. enable the on-chip voltage supply monitor and enable the voltage supply monitor as a reset source as early in code as possible. this should be the first set of instructions executed after the reset vector. for c- based systems, this will involve modify ing the startup code in the precision32 hal. ensure that there are no delays in software between enabling the voltage supply monitor and enabling the voltage supply monitor as a reset source. 4. as an added precaution, explicitly enable the voltag e supply monitor and enable the voltage supply monitor as a reset source inside the functions that write and erase flash memory. the voltage supply monitor enable instructions should be placed at the beginning of the flash wr ite and erase functions. 5. ensure that all writes to the reseten register explicitly set the vm onren bit to a 1. areas to check are initialization code, which enables other reset sources, such as the missing clock detector or comparator, and instructions that force a so ftware reset. a global search on ?reseten? can quickl y verify this. 6. if the device has a high and low threshold setting for the voltage supply monitor, enable the high setting. the following sections show how to enable the voltage supply monitor, enable the voltage supply monitor as a reset source, and enable the high threshold setting where applicable using both hal and non-hal methods on various device families. 5.1.1. sim3cxxx/sim3u1xx/sim3l1xx devices enable voltage supply monitor: si32_vmon_0->control.vmonen = 1; // non-hal si32_vmon_a_enable_vdd_supply_monitor(si32_vmon_0); // hal enable voltage supply monitor as a reset source: si32_rstsrc_0->reseten.vmonren = 1; // non-hal si32_rstsrc_a_enable_vdd_monitor_reset_source(si32_rstsrc_0); // hal enable the high voltage monitor threshold:
AN694 8 rev. 0.1 si32_vmon_0->control.vddhithen = 1; // non-hal si32_vmon_a_select_vdd_high_threshold(si32_vmon_0); // hal 5.2. ahb clock 1. if operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and changes in temperature. if the system is operating in an electrically noisy environment, use one of the internal oscillato rs or an external cmos clock. 2. if operating from the ex ternal oscillator, switch to one of the internal oscillato r during flash write or erase operations. the external oscillator can continue to run, and the core can switch back to the external oscillator after the flash operation completes.
AN694 rev. 0.1 9 n otes :
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